The invention relates to a system for (1) speed control circuitry allowing the microprocessor access to both fast and slow memories and I/O interface to effectuate automatic reduction of overall system power and (2) determining program execution location.
Microprocessors generally contain an internal address bus, an internal data bus, a number of registers including an accumulator, a program counter, an internal data latch, stack pointer registers, index registers, an arithmetic logic unit, an instruction register, a status register, instruction decoding circuitry, register transfer logic, and data buffer latches and address latches. Microprocessors do not ordinarily contain additional components that are needed in a microcomputer system, such as a read only memory for storing programs, a random access memory for storing variables and data, timers, UARTs, I/O functions, priority interrupt systems and the like. However, with the wide availability and commercial success of quite a number of microprocessors, various suppliers have begun using commercially available microprocessor designs as "embedded" cores of larger microcontrollers or microcomputers on single silicon chips that include not only the microprocessor, but also some or all of the above-mentioned components and other components.
Occasionally, it is desirable to provide a PCMCIA card or an EPROM which includes a complete application program and to have execution of the program controlled entirely by such PCMCIA card or EPROM. In one prior art device marketed by Infopak, Inc. of Phoenix, Ariz., application programs were stored in a PCMCIA card. The PCMCIA card constituted the memory of the microprocessor, which was a W65816 with no on-chip ROM so the PCMCIA card had to be plugged in before the computer could be powered up. Therefore, the entire application was automatically executed "in place" under the control of the PCMCIA card. However, that system allows no selection of the relative priorities of executing various applications that may be stored in various memories or sections of memory in the computer system. The computer into which such PCMCIA card is inserted becomes, in effect, an inflexible, dedicated computer as long as the PCMCIA card is plugged in and can perform no other function than to execute the program stored in the PCMCIA card.
In some applications of a microcomputer it may be desirable to access off-chip memory, such as slow EPROM, SRAM or DRAM and fast on-chip SRAM and SROM. It would be very desirable for the entire microcomputer to be able to automatically operate at various fast and slow speeds while accessing various on-chip and off-chip memories and/or peripheral devices, because many applications of microcomputers require use of battery power, and consequently it would be very desirable for microcomputers used in such applications to be able to automatically minimize the system power consumption according to the demands of the program or routines currently being executed. Conventional computers continue to operate at a fast cycle rate during a slow memory access, using wait states or the like to effectuate accessing of slower blocks of memory to allow the processor to continue to perform functions.
The closest prior art known to me includes the above-mentioned Infopak system and the W65C134S microcontroller which is fully described in U.S. Pat. No. 5,123,107. I designed and now market the W65C134S microcontroller through my company, The Western Design Center, Inc. of Mesa, Ariz.
There is a presently unmet need for a more powerful microcomputer chip that can operate with lower power consumption than previously has been practical. There also is a presently unmet need for a low cost computer that is able to allow easy prioritization of "in-place" execution of a plurality of programs in various memory devices on the basis of permanent instructions resident in the microcomputer chip.